 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| SPICE Device Model SUM50N03-13LC Vishay Siliconix N-Channel 30-V (D-S) 175C MOSFET with Sense Terminal CHARACTERISTICS * N-Channel Vertical DMOS * Macro Model (Subcircuit Model) * Level 3 MOS * Apply for both Linear and Switching Application * Accurate over the -55 to 125C Temperature Range * Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached spice model describes the typical electrical characteristics of the n-channel vertical DMOS. The subcircuit model is extracted and optimized over the -55 to 125C temperature ranges under the pulsed 0 to 10V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 71918 09-Jun-04 www.vishay.com 1 SPICE Device Model SUM50N03-13LC Vishay Siliconix SPECIFICATIONS (TJ = 25C UNLESS OTHERWISE NOTED) Parameter Static Gate Threshold Voltage On-State Drain Current a Symbol Test Conditions Simulated Data 1.8 434 0.010 0.016 0.018 0.014 0.90 Measured Data Unit VGS(th) ID(on) VDS = VGS, ID = 250 A VDS = 5 V, VGS = 10 V VGS = 10 V, ID = 25 A V A 0.010 0.016 0.018 0.014 1.3 V Drain-Source On-State Resistancea rDS(on) VGS = 10 V, ID = 25 A, TJ = 125C VGS = 10 V, ID = 25 A, TJ = 175C VGS = 4.5 V, ID = 24 A Forward Voltagea VSD IS = 50 A, VGS = 0 V Dynamic b Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Chargec Gate-Source Chargec Gate-Drain Chargec Turn-On Delay Timec Rise Timec Turn-Off Delay Timec Fall Time c Ciss Coss Crss Qg Qgs Qgd td(on) tr td(off) tf trr IF = 50,A di/dt = 100 A/s VDD = 15 V, RL = 0.30 ID 50 A, VGEN = 10 V, RG = 2.5 VDS = 15 V, VGS = 10 V, ID = 50 A VGS = 0 V, VDS = 25 V, f = 1 MHz 2009 367 111 34 7.6 5.6 23 19 8 10 29 1960 380 180 35 7.6 5.6 10 93 30 10 35 ns nC pF Reverse Recovery Time Notes a. Pulse test; pulse width 300 s, duty cycle 2%. b. Guaranteed by design, not subject to production testing. c. Independent of operating temperature. www.vishay.com 2 Document Number: 71918 09-Jun-04 SPICE Device Model SUM50N03-13LC Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ=25C UNLESS OTHERWISE NOTED) Document Number: 71918 09-Jun-04 www.vishay.com 3 |
Price & Availability of SUM50N03
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |